Note: The job is a remote job and is open to candidates in USA. TylSemi is a company focused on building chiplet infrastructure IP for AI and HPC systems. They are seeking a Technical Program Manager to oversee customer engagements and ensure precision in connecting strategic initiatives with the semiconductor supply chain.
Responsibilities
- Manage all active customer engagements end-to-end: from architectural spec alignment through tape-out, KGD testing, packaging, and volume shipment milestones
- Ensure alignment with ecosystem partners — including foundries, OSAT/packaging houses, EDA vendors (Synopsys, Cadence), and IP partners
- Translate customer requirements (silicon architecture, interface specs, package form factor, delivery schedules) into internal program plans with clear owners and dates
- Build and maintain program trackers, risk registers, and executive dashboards covering each engagement
- Drive gate reviews and weekly program syncs across internal RTL/DV, physical design, and validation teams
- Manage internal and external scoping and delivery timelines in coordination with technical and business teams
- Identify and escalate risks early; propose and implement mitigations before they become schedule threats
Skills
- 15+ years of technical program or project management experience in semiconductor, custom silicon, or chiplet/advanced packaging environments
- Direct experience interfacing with ecosystem partners — chip development schedules, interdependencies on EDA and IP, tape-out schedules and silicon bring-up timelines
- Familiarity with silicon fabrication, advanced packaging formats: CoWoS, InFO, 2.5D/3D integration, substrate/interposer-based assembly
- Technical fluency in SoC or chiplet design flows — enough to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases without needing translation
- Strong communication skills — comfortable presenting program status and risk posture to internal and external stakeholders
- Proficiency with program tracking tools (and spreadsheet-based trackers); experience building program infrastructure from scratch is a plus
- Familiarity with key connectivity IPs UCIe, PCIe Gen 5/6/7+, or high-bandwidth D2D interconnect standards is a strong plus
- Prior experience at a chiplet startup, merchant silicon company, or systems company
- Background in AI/ML infrastructure silicon — accelerators, network switches, CPO-enabled platforms
- Familiarity with IVR/PMIC integration challenges in advanced packaging
- Exposure to EDA infrastructure programs (SNPS/CDNS cloud flows)
Company Overview